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Developer Source 4
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auza1f3.gif
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Graphics Interchange Format
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1996-06-19
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54KB
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451x396
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FIGURE 3 Intel386 EX block diagram. Programmable Chip-Selects (8) Bus Interface 26 Addr. 16 Data DMA (2 Channels) Timer/Counter (3 Channels) Static 386 SX Core 2.7V - 5.5V Interrupt Controller (Two 82C59s) Async. SIO (2 Channels) Extended Temp. A20 Gate Sync. SIO(1 Channel) Full Duplex Intermodule Bus System Management Mode DRAM Refresh Clock Generation & Watchdog Timer (H/W, SAWV) Power Management JTAG Boundary scan Parallel I/O (Up to 24 lines)